1. Technical Field
The present disclosure relates to memory controllers, and more specifically to processing of read requests in a memory controller using pre-fetch mechanism.
2. Related Art
A memory controller refers to a component which receives access requests (read requests, write requests, etc.) directed to a memory (e.g., DRAM), and forwards the access requests to the memory. In case of read requests, the memory controller may receive the retrieved data as a response and forwards the retrieved data to components (requesters) from which the read request is received.
In a typical configuration, multiple requesters (such as a central processing unit, graphics controller, external peripherals, etc.) send access requests on a bus and receive corresponding responses also on the bus.
Memory controllers often rely on pre-fetch mechanism in processing read requests. Pre-fetch generally refers to retrieval of data, which is not specifically requested in presently being processed read requests. In general, pre-fetching is performed with a view to immediately providing response to any later received read requests, which request the pre-fetched data.
Thus, a cache is often used to store pre-fetched data and the cache is examined for matching data and if a match is found, the data from the cache is immediately sent to the requester. As a result, responses to such read requests (when match is found) may be provided with reduced delay/latency.
It is generally desirable that such pre-fetch mechanism be supported with one or more of requirements such as reduced latency for at least some types of read requests, avoidance of delay for other requesters, etc.